Dual-mode clock for improved power management in a wireless device

ABSTRACT

A dual mode clock for providing first and second clock signals to a wireless interface unit. The first and second clock signals correspond to first and second operating states of the wireless interface unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having low phase-noise characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a quality sufficient to maintain efficient operation of the digital baseband module in the wireless interface. By switching between low-power mode and normal mode, the system is operable to provide a high quality clock signal for use by the RF analog module when it is operational and to provide a lower power, lower quality clock signal which is sufficient for use by the baseband digital unit when the transceiver in the RF analog module is powered down.

BACKGROUND

[0001] 1. Technical Field

[0002] The present invention relates generally to digital computers; andmore particularly to wireless interface devices coupled to digitalcomputers.

[0003] 2. Related Art

[0004] Wireless communication technology has advanced rapidly over thepast few years. One of the most promising areas for the use of wirelesstechnology relates to communications between input/output devices andtheir “host” computers. For example, wireless keyboards and mice nowcouple via wireless connections to their host computers. These“wireless” input devices are highly desirable since they do not requireany hard-wired connections with their host computers. However, the lackof a wired connection also requires that the wireless input devicescontain their own power supply, i.e., that they be battery powered. Inorder to extend the life of their batteries, the wireless input devicesoften support power saving modes of operation. Some techniques forconserving power, however, can cause degradation in the performance ofvarious system components in the wireless interface.

[0005] The various components in a wireless interface device havedifferent operating requirements for the clock signals used for theiroperation. For example, the analog module typically requires a highquality clock signal with very low phase-noise. The digital module,however, can generally be operated efficiently with a clock signalhaving a higher phase-noise without serious degradation in performance.Generating a clock signal with the higher quality, low phase-noisecharacteristics required by an analog module requires more power than isrequired to generate a clock signal having the quality parametersrequired for a digital module. If the analog section is not operating,therefore, it is possible to conserve power by generating a clock signalhaving quality parameters needed only by the digital module. It would bedesirable, therefore, to provide a wireless interface device having apower management system capable of conserving power by controlling theclock generator to provide different clock signals that are matched tothe specific operational requirements of the system at any time.

SUMMARY OF THE INVENTION

[0006] The dual mode clock of the present invention overcomesshortcomings of the prior art by providing a method and apparatus forproviding first and second clock signals to a wireless interface unit,with the first and second clock signals being generated at correspondingfirst and second power levels, depending on the operating mode of thewireless interface unit.

[0007] The wireless interface system of the present invention includes awireless interface unit, a processing unit, an input/output unit, and apower management unit. The power management unit operably couples to thewireless interface unit, the processing unit, and the input/output unit.The power management unit operates to control the power consumption ofthe wireless interface device and the processing unit. The powermanagement unit works in conjunction with a processing unit to determinewhether the wireless interface unit is operating in a first power modewherein a transceiver in a radio frequency module is operational or asecond power mode wherein the transceiver is turned off.

[0008] A clock generator operates in conjunction with the powermanagement unit, via a wireless interface unit voltage regulator, toprovide first and second clock signals corresponding to first and secondoperating states of the wireless interface device. In the firstoperating state, the transceiver in the RF analog module is operationaland the clock generator provides a first clock signal having lowphase-noise characteristics necessary to maintain efficient operation ofthe transceiver. In a second operating state, the transceiver in the RFanalog module is turned off. In this second operational state, the clockgenerator provides a second clock signal having a quality sufficient tomaintain efficient operation of the digital baseband module in thewireless interface.

[0009] The baseband digital unit performs certain voltage regulatorfunctionality to assist in power management functions. A transmitteroperation detector and a voltage regulator control signal generatorwithin the baseband core are operable to detect operation of thetransceiver in the RF analog module and to generate a voltage regulatorreference control signal for use by the processing unit to process datafor the power management unit.

[0010] By switching between low-power mode and normal mode, the systemis operable to provide a high quality clock signal for use by the RFanalog module when it is operational and to provide a lower power, lowerquality clock signal which is sufficient for use by the baseband digitalunit when the transceiver in the RF analog module is powered down.

[0011] Moreover, other aspects of the present invention will becomeapparent with further reference to the drawings and specification, whichfollow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1A is a system diagram illustrating a PC host and a wirelessmouse that includes a wireless interface device constructed according tothe present invention.

[0013]FIG. 1B is a system diagram illustrating a PC host and a wirelesskeyboard that includes a wireless interface device constructed accordingto the present invention.

[0014]FIG. 2 is a schematic block diagram illustrating the structure ofa wireless mouse that includes a wireless interface device constructedaccording to the present invention.

[0015]FIG. 3 is a schematic block diagram illustrating the structure ofa wireless keyboard that includes a wireless interface deviceconstructed according to the present invention.

[0016]FIG. 4 is a block diagram illustrating a wireless interface device(integrated circuit) constructed according to the present invention.

[0017]FIG. 5A is a block diagram illustrating a first embodiment of awireless interface unit employing the dual mode clock system of thepresent invention.

[0018]FIG. 5B is a block diagram illustrating a second embodiment of awireless interface unit employing the dual mode clock system of thepresent invention.

[0019]FIG. 5C is a block diagram illustrating a third embodiment of awireless interface unit employing the dual mode clock system of thepresent invention.

[0020]FIG. 6 is a block diagram illustrating a processing unit of thewireless interface device of FIG. 4.

[0021]FIG. 7 is a block diagram illustrating an input/output unit of thewireless interface device of FIG. 4.

[0022]FIG. 8 is a block diagram generally showing the structure of anintegrated circuit constructed according to the present invention withparticular detail in the coupling of battery power to the units of thedevice.

[0023]FIG. 9 is a logic diagram illustrating operation according to thepresent invention.

[0024]FIG. 10 is a logic diagram illustrating operation according to thepresent invention in controlling the power consumption of a serviceddevice.

[0025]FIG. 11 is a flow chart illustrating the processing steps foroperating the embodiment of wireless interface unit shown in FIG. 5Ausing the dual mode clock of the present invention.

[0026]FIG. 12 is a flow chart illustrating the processing steps foroperating the embodiment of wireless interface unit shown in FIG. 5Busing the dual mode clock of the present invention.

[0027]FIG. 13 is a flow chart illustrating the processing steps foroperating the embodiment of wireless interface unit shown in FIG. 5Cusing the dual mode clock of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1A is a system diagram illustrating a PC host 102 and awireless mouse 104 that includes a wireless interface device constructedaccording to the present invention. As shown in FIG. 1A, the PC host 102wirelessly couples to the wireless mouse 104. In the structure of FIG.1A, the wireless mouse 104 includes a wireless interface device thatoperates to place the wireless mouse in any of a number of reduced poweroperating modes, including a power down mode in which battery life issubstantially extended.

[0029]FIG. 1B is a system diagram illustrating a PC host 106 and awireless keyboard 108 that includes a wireless interface deviceconstructed according to the present invention. The wireless keyboard108 is battery powered and operates for extended periods of time on asingle set of batteries because of the greatly reduced power consumptionoperations according to the present invention.

[0030]FIG. 2 is a schematic block diagram illustrating the structure ofa wireless mouse that includes a wireless interface device constructedaccording to the present invention. An integrated circuit 202constructed according to the present invention serves as the wirelessinterface device and couples to various mouse inputs 210. These mouseinputs 210 include x-axis and y-axis inputs as well as a scroll input.The x-axis and y-axis inputs are often referred to a “quadrature”inputs. The components that produce the quadrature inputs are generallyreferred to at numeral 212 and may be constructed from optical inputsinstead of from conventional mechanical inputs. Referenced via numeral214 are the button inputs that are typical with a computer mouse andinclude the left button input, the middle/scroll button input, and theright button input. As is shown, each of the signals produced by themouse are received by integrated circuit 202.

[0031] Integrated circuit 202 also couples to battery 204, crystal 206that produces a 12 MHz reference frequency, EEPROM 208, and antenna 216.In one embodiment of the present invention, battery 204 comprises a pairof either AA batteries or AAA batteries. Antenna 216 is an internalantenna in the described because of the size constraints of the mouseand because of the relatively short distance between the PC host and thewireless mouse.

[0032]FIG. 3 is a schematic block diagram illustrating the structure ofa wireless keyboard that includes a wireless interface device(integrated circuit 202) constructed according to the present invention.As shown in FIG. 3, integrated circuit 202 services a key scan matrix202 that provides inputs from the keyboard. Indicators 304 includenumber, capitals, and scroll lights that are lit on the keyboard. Theintegrated circuit 202 couples to a battery 204, a crystal 206, anEEPROM 208, and an antenna 216.

[0033] In another embodiment (not shown in either FIG. 2 or FIG. 3), theintegrated circuit 202 services both mouse and keyboard input and mayreside internal to either the mouse or the keyboard. As will be apparentto those skilled in the art, multiplexing or signal sharing may berequired, because the input signals differ. However, different signallines may be dedicated for keyboard and for mouse inputs such that nosignal sharing is required. As is apparent, when the integrated circuit202 alone services both mouse and keyboard, input wired connectivitybetween the keyboard and the mouse is required.

[0034]FIG. 4 is a block diagram illustrating a wireless interface device(integrated circuit) constructed according to the present invention. Asshown in FIG. 4, the wireless interface device 400 includes a processingunit 402, a wireless interface unit 404, an input/output unit 406, and apower management unit 408. The wireless interface unit 404 couples thewireless interface device 400 to antenna 216. The wireless interfaceunit 404 can be adapted to operate according to the Bluetoothspecification and in particular to the Human Interface Device (HID)portion of the Bluetooth specification. It will be understood by thoseskilled in the art, however, that the present invention can be adaptedto work in conjunction with other wireless interface standards.

[0035] Processing unit 402, wireless interface unit 404, andinput/output unit 406 couple with one another via a system on chip (SOC)bus 410. Processing unit 402 includes a processing interface that may beused to couple the processing unit to one or more devices. Input/outputunit 406 includes an input/output set of signal lines that couple thewireless interface device 400 to at least one user input device, such asa mouse or the keyboard incorporating the improved scan circuitdescribed hereinbelow.

[0036]FIG. 5A is a block diagram illustrating a wireless interface unitof the wireless interface device of FIG. 4. The wireless interface unit404 includes a transmit/receive switch 502, a radio frequency module 503that comprises a 2.4 GHz transceiver 504, a baseband core 506 which maybe compatible with the Bluetooth standard and a clock generator 508.Each of these components is generally known in the field and will bedescribed in minimal detail herein.

[0037] The transmit/receive switch 502 couples to antenna 216 andswitches between transmit and receive operations. The 2.4 GHztransceiver 504 performs all RF front-end operations and operates withina frequency band and on particular channels as are specified by theBluetooth operating standard. The 2.4 GHz transceiver 504 couples tobaseband core 506. Such coupling is performed via an RF controlinterface and an RF data interface. The RF control interface performsthe necessary control operations to guaranty that the 2.4 GHztransceiver 504 and the baseband core 506 will operate consistentlywithin desired operating specifications. The RF data interface transfersboth Rx and Tx data between the 2.4 GHz transceiver 504 and the basebandcore 506. Clock generator 508 comprises a bias generator 509 and anoscillator 510 that couples to the external crystal 206 operating at 12MHz, and to the frequency synthesizer 512. The clock generator 508 iscontrolled to provide an RF frequency for the 2.4 GHz transceiver 504which is used to mix with the baseband signal received from the basebandcore during a transmit operation and to mix with the received RF signalduring a receive operation. The clock generator 508 operates inconjunction with the power management unit 408, via the wirelessinterface unit voltage regulator 520, to provide different clock signalscorresponding to different power states as discussed hereinbelow.

[0038] The baseband digital unit performs certain voltage regulatorfunctionality to assist in power management functions. A transceiveroperation detector 516 and a voltage regulator control signal generator518 within the baseband core 506 cooperate to detect operation of thetransceiver in the RF analog module 503 and to generate a voltageregulator reference control signal for use by the processing unit 402 toprocess data for the power management unit 408.

[0039] The frequency synthesizer 512 produces a high quality, lowphase-noise clock signal for operation of the analog section of the RFanalog module 503. As discussed herein, a power management unit 408 isoperable to provide power at varying power levels depending on theoperating mode of the system. A “low-power mode” control signal is usedto cause the power management unit to switch between dual operatingmodes, thereby controlling power to the RF module 503 and the clockgenerator 508, depending on the specific operating mode.

[0040] When the low-power mode (LPM) signal shown in FIGS. 5A-C is“low,” the system operates in “normal” mode. When the LPM signals goes“high,” the system enters a low-power mode. In the low-power down mode,the RF analog module 503 is turned off and the frequency synthesizer 512is also turned off. The oscillator 510 is switched to a low-power mode,which generates a clock signal of sufficient quality to control thebaseband digital core 506. When the LPM signal goes low, the systemreturns to normal mode whereby the bias generator 509 provides a higherpower bias signal to the clock generator 508, thereby allowing the clockgenerator to generate a higher quality clock signal for use by thefrequency synthesizer 512.

[0041] By switching between low-power mode and normal mode, the systemis operable to provide a high quality clock signal for use by the RFanalog module 503 when it is operational and to provide a lower power,lower quality clock signal which is sufficient for use by the basebanddigital unit 506 when the transceiver 504 and frequency synthesizer 512in the RF analog module 503 are powered down.

[0042]FIG. 5B is an illustration of an alternate embodiment of the dualmode clock of the present invention. In this embodiment, the clocksignal output of the clock generator 508 is provided to the frequencysynthesizer 512. However, no clock signal is provided directly from theclock generator to the baseband digital core 506. In this embodiment,the frequency synthesizer in the RF analog module 503 generates a lowphase-noise clock for the transceiver 504. In addition, the output ofthe frequency synthesizer 512 is also used to generate a clock signalfor the baseband digital core 506. Again, when the LPM signal is low,the system operates in “normal” mode. When the LPM signal goes high, thesystem enters a low-power mode. In the power down mode, the transceiver504 in the RF analog module 503 is turned off. The frequency synthesizer512, however, continues to run, thereby providing a clock signal to thebaseband digital core 506. When operating in the power down mode, thebias generator 509 provides a lower power bias signal to the oscillator510 in the clock generator 508.

[0043] Operation of the embodiments of FIGS. 5A-C will be discussedbelow in connection with the flowcharts of FIGS. 11-13.

[0044]FIG. 5C is an illustration of another alternate embodiment of thedual mode clock of the present invention. In this embodiment, theoscillator 510 provides a clock signal to the frequency synthesizer 512.The frequency synthesizer 512 provides a high quality, low phase-noiseclock signal for the RF analog module 503 and also provides a clocksignal for the baseband digital core 506. The clock signal generated bythe frequency synthesizer 512 for use by the baseband digital core 506,however, is provided as an input to a multiplexer 522, rather than beingprovided directly to the baseband core 506. When the LPM signal is low,the system operates in normal mode with both the transceiver 504 in theRF analog module 503 and the baseband digital core 506 receiving clocksignals from the frequency synthesizer 512. When the LPM signal goeshigh, however, the system enters a low-power mode wherein thetransceiver 504 in the RF analog section 503 is turned off and the biasgenerator 509 sends a lower power bias signal to oscillator 510,switching 510 to low-power mode. In the low-power down, the clock sourcefor the baseband digital core 506 is switched from the frequencysynthesizer 512 to the oscillator 510. A power down mode transitionsignal 118 from the power management unit 408 is used to control themultiplexer 522 to switch between the clock signal generated by thefrequency synthesizer 512 and the oscillator 510. At the same time, theprocessing unit 402 controls bias generator 509 to adjust the powerconsumption of clock generator 508.

[0045]FIG. 6 is a block diagram illustrating a processing unit 402 ofthe wireless interface device of FIG. 4. The processing unit 402includes a microprocessor core 602, read only memory 606, random accessmemory 604, serial control interface 608, bus adapter unit 610, andmultiplexer 612. The microprocessor core 602, ROM 606, RAM 604, serialcontrol interface 608, bus adapter unit 610, and multiplexer 612 couplevia a processor on a chip bus. Multiplexer 612 multiplexes an externalmemory interface between the processor on a chip bus and a test bus. Thebus adapter unit 610 interfaces the processor on a chip bus with theSOC. The microprocessor core 602 includes a universal asynchronousreceiver transmitter interface that allows direct access to themicroprocessor core. Further, the serial control interface 608 providesa serial interface path to the processor on a chip bus.

[0046]FIG. 7 is a block diagram illustrating an input/output unit 406 ofthe wireless interface device of FIG. 4. The input/output unit 406includes a keyboard scanning block 702, a mouse quadrature decoder block704, and a GPIO control block 706. Each of the keyboard scanning block702, the mouse quadrature decoder block 704 and the GPIO control block706 couple to the SOC bus. Further, each of the keyboard scanning block702, the mouse quadrature decoder block 704, and the GPIO control block706 couple to I/O via multiplexer 708. This I/O couples to the at leastone user input device.

[0047] In another embodiment of the input/output unit 406, each of thekeyboard scanning block 702, the mouse quadrature decoder block 704, andthe GPIO control block 706 couples directly to external pins that coupleto the at least one user input device.

[0048]FIG. 8 is a block diagram generally showing the structure of anintegrated circuit constructed according to the present invention withparticular detail in the coupling of battery power to the units of thedevice. Integrated circuit 800 of FIG. 8 includes a wireless interfaceunit 404, processing unit 402, input/output unit 406, and powermanagement unit 408. The processing unit 402, wireless interface unit404, and input/output unit 406 couple via a SOC bus 410. Further, as waspreviously described, input/output unit 406 couples to at least one userinput device via I/O connection.

[0049] With the integrated circuit 800 of FIG. 8, a pad ring 814surrounds a substantial portion of the components of the integratedcircuit. The pad ring 814 couples directly to battery 204, which powersthe pad ring. Further, input/output unit 406 and power management unit408 couple directly to pad ring 814 to receive their power and voltage.However, processing unit 402 couples to pad ring 814 via processing unitvoltage regulation circuitry 812. Further, the wireless interface unit404 couples to pad ring 814 via wireless interface unit voltageregulation circuitry 520. The processing unit voltage regulationcircuitry 812 is controlled by the power management unit 408 via controlsignal PU_EN. Further, the wireless interface unit voltage regulationcircuitry 520 is controlled by the power management unit 408 usingcontrol signal WIU_EN.

[0050] The integrated circuit operates in four differentpower-conserving modes: (1) busy mode; (2) idle mode; (3) suspend mode;and (4) power down mode. Busy mode, idle mode, and suspend mode aredescribed in the Bluetooth specification. However, power down mode isunique to the present invention.

[0051] In busy mode, the Master (host computer) is actively polling theHID (wireless mouse, wireless keyboard, etc.) for data at a polling ratenear 100 polls/second, or about once every 16 slot times. Continued useractivity (keypad strokes, mouse motion, button presses, etc.) keeps theHID in busy mode. If there has been no activity for a few seconds(determined by particular settings), operation transitions to idle mode.

[0052] In idle mode, the HID requests the master (serviced host) toenter SNIFF mode with a SNIFF interval that is chosen based on desiredlatency and average power consumption. In one operation, the SNIFFinterval is 50 ms, or about every 80 slot times. Although the HID canI/O Active immediately after an event, it may have to wait up to 100 mSto transmit its data to the host, and therefore must have enough bufferspace to store 100 mS of events. If an event occurs, the HID requeststhe master to leave SNIFF mode. If there is no further activity for alonger period, the HID transitions from idle mode to suspend mode. Then,the HID is parked.

[0053] In suspend mode, a longer beacon interval can be used for a lowerpower state. When in suspend mode, any user input detected will resultin the HID requesting to be unparked and transitioned back to the busymode. When the HID is parked, it consumes less power than when the hostis in SNIFF mode since the HID does not have to transmit. In suspendmode, the HID just listens to the beacons to remain synchronized to themaster's frequency hopping clock. As long as the master continuestransmitting (meaning the host is not turned off) the HID will remain insuspend mode. If link loss occurs due to the host being turned offwithout warning, or the host moving out of range, the Lost Link statewill be entered.

[0054] According to the present invention, the power down mode is alsosupported. In the power down mode, the power management unit 408operates the processing unit voltage regulation circuitry 812 and thewireless interface unit voltage regulation circuitry 520 to power downthe processing unit 402 and wireless interface unit 404, respectively.These states of operation will be described further with reference toFIGS. 9 and 10.

[0055]FIG. 9 is a logic diagram illustrating operation according to thepresent invention. As illustrated in FIG. 9, a wireless interface deviceoperating according to the present invention operates in four separatepower-conserving modes. These power conservation modes include the busymode, the idle mode, the suspend mode and the power down mode. The statediagram of FIG. 9 shows how each of these modes is reached during normaloperation.

[0056] When the wireless interface device is initially powered up, itenters the busy mode of operation. In the busy mode of operation, allfeatures and wireless operations of the wireless interface device areenabled. As long as I/O activity continues, the wireless interfacedevice remains in the busy mode. However, after expiration of a firsttimer with no I/O activity, the operation moves from the busy mode tothe idle mode. Operation will remain in idle mode until the expirationof a second timer or until I/O activity occurs.

[0057] If while in the idle mode I/O activity occurs, operation returnsto the busy mode. If in the idle mode, if timer 2 expires with noadditional I/O activity, suspend mode is entered. While in suspend mode,if I/O activity occurs, operation returns to busy mode. However, if insuspend mode, no additional I/O activity occurs until the expiration ofa third timer, power down mode is entered. While in the power down mode,operation will remain in the power down mode until I/O activity occurs.When I/O activity occurs, operation of the wireless interface devicewill move from the power down mode to the busy mode.

[0058]FIG. 10 is a logic diagram illustrating operation according to thepresent invention in controlling the power consumption of a serviceddevice. As shown in FIG. 10, once operation in a particular powerconservation state, e.g., busy mode, idle mode, suspend mode, and powerdown mode has commenced, operation will remain in that state untilexpiration of respective timer or I/O activity occurs (step 902).

[0059] When power conservation operation occurs to move from the busymode to the idle mode (step 902), all portions of the wireless interfacedevice remain powered (step 904). However, in the idle mode, thewireless interface unit enters a sniff mode in which some of itsoperations are reduced. Such operations were previously described withreference to FIG. 9. Further, additional information regarding this modeis available in the Bluetooth HID standard.

[0060] When the operation of the wireless interface device transitionsfrom the idle mode to the suspend mode (step 908), all portions of thewireless interface device remain powered (step 910). However, thewireless interface unit of the wireless interface device enters the parkmode, which consumes even less power than does the wireless interfaceunit when in the sniff mode.

[0061] When in the suspend mode if an additional timer or inactivityperiod expires, the wireless interface device will transition to thepower down mode (step 914). In the power down mode, the processing unitand wireless interface unit will be powered down (step 916). This powerdown operation will be performed in one embodiment by simplydisconnecting a voltage source from the processing unit in the wirelessinterface unit. One such technique for doing this is described withreference to FIG. 8. In the power down mode, the I/O unit will continueto be powered to allow it to sense the state of the user input devicelines.

[0062] Finally, from any of the reduced power operating states, when I/Oactivity is sensed by the I/O block, the wireless input device willtransition back to the busy mode (step 920). When such operation occurs,if the components have been powered down, they will be a powered up andwill go through their boot operations (step 922). Then, in the busymode, the wireless interface unit will operate in its normal state inwhich the master wireless device, i.e., wirelessly enabled host willpoll the wireless interface device at 100 times per second. From each ofsteps 906, 912, 918, and 924, operation returns to step 902 wherein thecurrent power conservation state will be kept until another eventoccurs.

[0063] Operation of the dual mode clock embodiment illustrated in FIG.5A can be understood by referring to the processing steps shown in theflowchart of FIG. 11. In step 1102, the system enters the normal mode ofoperation wherein the oscillator 510 provides a clock signal directly tothe baseband digital core 506 and to the frequency synthesizer 512 inthe RF analog module 503 as discussed hereinabove. In step 1104, thestatus of the low-power mode signal, LPM, is inspected. If the LPMsignal is low, processing returns to step 1102 wherein the normal modeof operation is continued. If, however, the test in step 1104 indicatesthat the LPM signal is high, processing proceeds to step 1106 where thetransceiver 504 in the RF analog module 103 is turned off and thefrequency synthesizer 512 is turned off in step 1108. In step 1110 theoscillator is switched to low-power mode and processing proceeds to step1112 where the system is operating in low-power mode. In step 1114, atest is conducted to determine whether the state of the LPM signal haschanged. If the test conducted in step 1114 indicates that the LPMsignal remains high, processing returns to step 1112 and the systemcontinues to operate in the low-power mode. If, however, the testconducted in step 1114 indicates that the LPM signal has transitionedfrom high to low, the system performs a power up sequence in step 1116and processing returns to step 1102 wherein the system operates in anormal mode of operation.

[0064] Operation of the alternate embodiment of the dual mode clockillustrated in FIG. 5B can be understood from the processing stepsillustrated in the flowchart of FIG. 12. In step 1202, the system entersthe normal mode of operation wherein the oscillator 510 provides a clocksignal directly to the baseband digital core 506 and to the frequencysynthesizer 512 in the RF analog module 503 as discussed hereinabove. Instep 1204, the status of the low-power mode signal LPM, is inspected. Ifthe low-power mode signal is low, processing returns to step 1202wherein the normal mode of operation is continued. If, however, the testin step 1204 indicates that the LPM signal is high, processing proceedsto step 1206 where the transceiver 504 in the RF analog module 503 isturned off. In step 1208 the oscillator is switched to low-power modeand processing proceeds to step 1210 where the system is operating inlow-power mode. In step 1212, a test is conducted to determine whetherthe state of the LPM signal has changed. If the test conducted in step1212 indicates that the LPM signal remains high, processing returns tostep 1210 and the system continues to operate in the low-power mode. If,however, the test conducted in step 1212 indicates that the low-powermode signal has transitioned from high to low, the system performs apower up sequence in step 1214 and processing returns to step 1202wherein the system operates in a normal mode of operation.

[0065] Operation of the alternate embodiment of the dual mode clockillustrated in FIG. 5C can be understood from the processing stepsillustrated in the flowchart of FIG. 13. In step 1302, the system entersthe normal mode of operation wherein the oscillator 510 provides a clocksignal directly to the baseband digital core 506 and to the frequencysynthesizer 512 in the RF analog module 503 as discussed hereinabove. Instep 1304, the status of the low-power mode, LPM, is inspected. If theLPM signal is low, processing returns to step 1302 wherein the normalmode of operation is continued. If, however, the test in step 1304indicates that the LPM signal is high, processing proceeds to step 1306where the transceiver 504 in the RF analog module 503 is turned off. Instep 1308 the oscillator is switched to low-power mode and processingproceeds to step 1310 where the oscillator operates as the source forthe baseband clock. The frequency synthesizer 512 is turned off in step1312 and processing proceeds to step 1314 where the system is operatingin low-power mode. In step 1316, a test is conducted to determinewhether the state of the LPM signal has changed. If the test conductedin step 1316 indicates that the LPM signal remains high, processingreturns to step 1314 and the system continues to operate in thelow-power mode. If, however, the test conducted in step 1316 indicatesthat the low-power mode signal has transitioned from high to low, thesystem performs a power up sequence in step 1318 and processing returnsto step 1302 wherein the system operates in a normal mode of operation.

[0066] In the embodiments shown in FIGS. 5A, 5B, and 5C, describedhereinabove, the clock generator is switched between normal mode andlow-power mode by varying the power bias delivered to the oscillatorcircuit. A further alternate embodiment of the clock generator 508 shownin FIGS. 5A, 5B, and 5C, is shown in FIG. 5D. This embodiment employstwo oscillator elements, 510A and 510B, which are enabled mutuallyexclusively. Oscillator 510A is designed such that it outputs ahigh-quality, low phase-noise clock signal, and operates at a higherpower level than oscillator 510B. Oscillator 510B is designed to operateat a lower power level than oscillator 510A, while outputting a lowerquality, higher phase-noise clock signal. The enable input, ENB, ofoscillator 510B is driven directly by the low-power mode signal, LPM.The enable input of oscillator 510A is driven by digital inverter 511which is in turn driven by the LPM signal. Both oscillator 510A andoscillator 510B are designed such that, when the ENB signal is drivenlow, the oscillator becomes inert, and does not significantly affect theoperation of the other oscillator.

[0067] When the system is operating in normal mode, and the processingunit 402 drives LPM low, oscillator 510A is enabled while oscillator510B is disabled. In this mode, oscillator 510A outputs a high quality,low phase-noise clock signal while operating at a higher power level.

[0068] When the system is operating in low-power mode, and theprocessing unit 402 drives LPM high, oscillator 510B is enabled whileoscillator 510A is disabled. In this mode, oscillator 510B outputs alower quality, higher phase noise clock signal while operating at a lowpower level.

[0069] One skilled in the art will recognize that the alternate clockgenerator embodiment shown in FIG. 5D and described hereinabove can beapplied to each of the system architectures shown in FIGS. 5A, 5B, and5C.

[0070] The invention disclosed herein is susceptible to variousmodifications and alternative forms. Specific embodiments, therefore,have been shown by way of example in the drawings and detaileddescription. It should be understood, however, that the drawings anddetailed description thereto are not intended to limit the invention tothe particular form disclosed, but on the contrary, the invention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the claims.

1. A system for managing power in a wireless interface system thatservices communications between a wirelessly enabled host and at leastone user input device, comprising: a wireless interface unit thatwirelessly interfaces with the wirelessly enabled host; a clockgenerator operable to generate first and second clock signalscorresponding to first and second operating states of the wirelessinterface unit; a processing unit operably coupled to the wirelessinterface unit; and a power management unit operably coupled to thewireless interface unit, the processing unit, and the clock generator,wherein the power management unit controls the power consumption of thewireless interface device by providing a first power level to the clockgenerator when the wireless interface unit is in the first operatingstate and providing a second power level to the clock generator when thewireless interface unit is in the second operating state.
 2. Thewireless interface device of claim 1, wherein: the wireless interfaceunit comprises an analog module and a digital module; and wherein duringthe first operating state the analog module is fully operational andduring the second operating state the analog module is in a reducedpower mode and is not fully operational.
 3. The wireless interface unitaccording to claim 1, wherein the clock generator comprises first andsecond oscillator modules, and wherein the first oscillator module isoperational when the clock generator is generating the first clocksignal and wherein the second oscillator module is operational when theclock generator is generating the second clock signal.
 4. The wirelessinterface device of claim 1, further comprising processing unit voltageregulation circuitry that couples the processing unit to a voltagesource, wherein the power management unit controls the operation of theprocessing unit voltage regulation circuitry to controllably power theprocessing unit.
 5. The wireless interface device of claim 1, whereinthe wireless interface device enters one of a plurality of powerconsumption operating states comprising: busy mode in which allcomponents of the wireless interface device are powered and operational;idle mode in which the wireless interface unit performs first powerconserving operations; suspend mode in which the wireless interface unitperforms second power conserving operations; and power down mode inwhich the wireless interface unit and the processing unit are powereddown.
 6. A system for managing power in a wireless interface system thatservices communications between a wirelessly enabled host and at leastone user input device, comprising: a wireless interface unit thatwirelessly interfaces with the wirelessly enabled host, wherein thewireless interface unit comprises an analog module including atransceiver unit, a digital module further comprising: transmitteroperation detector operable to detect operation of the transceiver unit,and a voltage regulator control signal generator operable to generate avoltage regulator reference control signal corresponding to theoperational status of the transceiver; a clock generator operable togenerate first and second clock signals corresponding to a firstoperating state wherein the transceiver is operational and a secondoperating state wherein the transceiver is turned off; a processing unitoperably coupled to the wireless interface unit; and a power managementunit operably coupled to the wireless interface unit, the processingunit, and the clock generator, wherein the power management unitcontrols the power consumption of the wireless interface device byproviding a first power level to the clock generator when the wirelessinterface unit is in the first operating state and providing a secondpower level to the clock generator when the wireless interface unit isin the second operating state.
 7. The wireless interface unit accordingto claim 6, wherein the clock generator comprises first and secondoscillator modules, and wherein the first oscillator module isoperational when the clock generator is generating the first clocksignal and wherein the second oscillator module is operational when theclock generator is generating the second clock signal
 8. The wirelessinterface device of claim 7, during the first operating state the analogmodule is fully operational and during the second operating state theanalog module is in a reduced power mode and is not fully operational.9. The wireless interface device of claim 6, wherein the wirelessinterface device enters one of a plurality of power consumptionoperating states comprising: busy mode in which all components of thewireless interface device are powered and operational; idle mode inwhich the wireless interface unit performs first power conservingoperations; suspend mode in which the wireless interface unit performssecond power conserving operations; and power down mode in which thewireless interface unit and the processing unit are powered down. 10.The wireless interface device of claim 9, wherein in the idle mode thewireless interface unit periodically communicates with the wirelesslyenabled host.
 11. The wireless interface device of claim 9 wherein inthe suspend mode: the wireless interface unit does not transmit to thewirelessly enabled host; and the wireless interface unit listens to thetransmissions of the wirelessly enabled host.
 12. The wireless interfacedevice of claim 11, wherein the power management unit powers down thewireless interface unit and the processing unit after at least oneinactivity period during which the at least one user input device isinactive with respect to the input/output unit.
 13. The wirelessinterface device of claim 6, wherein the user input device includes acursor control device.
 14. The wireless interface device of claim 6,wherein the user input device includes a keypad.
 15. The wirelessinterface device of claim 6, wherein the user input device includes: acursor control device; and a keypad.
 16. A method for managing power ina wireless interface unit, comprising: generating first and second clocksignals from a clock generator, said clock generator being operable togenerate the first clock signal when the wireless interface unit is in afirst operating state and operable to generate the second clock signalwhen the wireless interface unit is in a second operating state;providing the first clock signal to the wireless interface unit when thewireless interface unit is in the first operating state; providing thesecond clock signal to the wireless interface unit when the wirelessinterface unit is in the second operating state; and using a powermanagement unit to control the clock generator by providing a firstoperating voltage to cause the clock generator to generate the firstclock signal and providing a second operating voltage to cause the clockgenerator to generate the second clock signal.
 17. The method of claim16, wherein: the wireless interface unit comprises an analog module anda digital module; and wherein during the first operating state theanalog module is fully operational and during the second operating statethe analog module is in a reduced power mode and is not fullyoperational.
 18. The method of claim 16, wherein the clock generatorcomprises first and second oscillator modules, and wherein the firstoscillator module is operational when the clock generator is generatingthe first clock signal and wherein the second oscillator module isoperational when the clock generator is generating the second clocksignal.
 19. The wireless interface device of claim 16, wherein thewireless interface device enters one of a plurality of power consumptionoperating states comprising: busy mode in which all components of thewireless interface device are powered and operational; idle mode inwhich the wireless interface unit performs first power conservingoperations; suspend mode in which the wireless interface unit performssecond power conserving operations; and power down mode in which thewireless interface unit and the processing unit are powered down.
 20. Anintegrated circuit that services communications with a wirelesslyenabled host and that services at least one user input device, theintegrated circuit comprising: a wireless interface unit that wirelesslyinterfaces with the wirelessly enabled host; a clock generator operableto provide first and second clock signals to the wireless interfaceunit, wherein the first clock signal corresponds to a first operatingstate of the wireless interface unit and the second clock signalcorresponds to a second operating state of the wireless interface unit;a processing unit operably coupled to the wireless interface unit; aninput/output unit operably coupled to the wireless interface unit and tothe processing unit, wherein the input/output unit also operably couplesto the at least one user input device; and a power management unitoperably coupled to the wireless interface unit, the processing unit,and the clock generator, wherein the power management unit controls thepower consumption of the wireless interface device by providing a firstpower level to the clock generator when the wireless interface unit isin the first operating state and providing a second power level to theclock generator when the wireless interface unit is in the secondoperating state.
 21. The integrated circuit of claim 20, wherein: thewireless interface unit comprises an analog module and a digital module;and wherein during the first operating state the analog module is fullyoperational and during the second operating state the analog module isin a reduced power mode and is not fully operational.
 22. The integratedcircuit of claim 20, wherein the clock generator comprises first andsecond oscillator modules, and wherein the first oscillator module isoperational when the clock generator is generating the first clocksignal and wherein the second oscillator module is operational when theclock generator is generating the second clock signal.
 23. Theintegrated circuit of claim 20, wherein the wireless interface deviceenters one of a plurality of power consumption operating statescomprising: busy mode in which all components of the wireless interfacedevice are powered and operational; idle mode in which the wirelessinterface unit performs first power conserving operations; suspend modein which the wireless interface unit performs second power conservingoperations; and power down mode in which the wireless interface unit andthe processing unit are powered down.